These can be two nodes within the same net, or they can be two nodes in associated nets separated by a component. This feature enables the correct treatment of a high-speed signal path as just that - a path for a signal to travel between a source and destination, through termination components as well as branches.Īn xSignal is essentially a designer-defined signal path between two nodes. This can be managed by a feature called xSignals (or e xtended Signal). This makes it difficult for the designer to specify key design requirements, such as Length and Matched Length design rules. As soon as a series termination resistor is added, that address line becomes two discrete nets. Even though address A0 passes through a termination resistor, to the designer, that signal is still A0 on the other side of that resistor.īut the PCB editor sees each signal simply as a set of connected pins (commonly referred to as a net) - Net A0 goes from this connector pin to this memory component pin, then to this memory component pin, and so on. I might also require a series terminator at the source'). To achieve that I'll route using a fly-by topology with a termination resistor at the end. Now the designer sees the signals in terms of their function (eg, 'This address signal must be routed from this connector to each memory device.
The designer's job is to translate their design requirements, such as the maximum route length allowed to meet the timing budget, into a set of design rules, such as a Length rule to ensure that the timing is met, and a Matched Length rule to detect potential timing mismatches. This is not the case for many typical design solutions though where there may be a series termination component in the signal path, or there are more than two pins in the signal, which could then be routed using a Balanced T or a Fly-By routing topology, as shown in the image below.įour DDR2 RAM chips routed using a Balanced T topology.
For a set of 2-pin signal paths, each running from an output pin to a single input pin, calculating and comparing the lengths is a straightforward process. The timing requirements are met by matching the routed lengths of the signal paths. The signal integrity can be managed through controlled impedance routing, which is achieved through the careful design of both the PCB stackup and the routing widths to be used on each layer. With ever-increasing device switching speeds comes the challenge of maintaining the integrity of the signal, and meeting the signal's timing requirements.
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